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Bit to Bipolar type.

Utilize the combination circuit.

Most of the current FPGA development is done in the pattern of "Synchronous circuit + Combinational circuit".
With the increase in speed and scale of FPGAs, the clock path in synchronous circuits has become longer, causing more timing errors and other problems.
Since the clock is the same for each step of the pipeline, it is necessary to adjust the frequency to the part of the pipeline with the longest processing time.
If the processing time for each step is significantly different, adjustments such as separating the steps will be necessary.
There is no clock equivalent in the human brain, which is currently the most sophisticated and flexible information system.
Information is processed between nerve cells by passing pulsed electrical signals and neurotransmitters.
Neurons transmit pulses, but there are no positive or negative pulses.
Computer-wise, only "1" is being sent intermittently.
And the frequency of the pulse transmission and the strength of the cell-to-cell coupling change the importance of the information.
In addition, there are some connections that cause excitation in the receiving nerve cell depending on the pulse between the two cells, and others that inhibit the excitation.

In digital electronic circuits, processing is usually done bit by bit.
A single bit can only take on two states, 1 and 0.
The half adder of the combinational circuit looks like this

The information comes in from the A and B terminals, and the calculation results are output to the S and C terminals.
There is a problem with this circuit.
Since a bit can only represent two states, 1 and 0, it cannot represent whether the information exists or not.
Therefore, this circuit cannot know when the operation is finished.

The solution is not to use bits as the smallest unit of information, but to use something that can represent the three states of "no information", "0", and "1".
This corresponds to the presence or absence of a pulse and the coupling of excitation and inhibition in the human brain, as mentioned earlier.
Since it is difficult to represent three types in an electronic circuit, we will use three of the four types as a set with two bits.
In SchemaHD, a set of information can be easily defined as an interface.
We defined it as a Bipolar type.

Name Number of Bits Directions Base interface
Bipolar 2    
   One 1 Forward One
   Zero 1 Forward Zero

The information flowing through the defined One and Zero is as follows
value state
0 The information doesn't exist.
1 The "1" information exists.

The country combination of Bipolar type One and Zero is as follows.
One Zero state
0 0 The information doesn't exist.
1 0 The "1" information exists.
0 1 The "0" information exists.
1 1 Not Used!

Created the basic logic elements BUFFER, NOT, AND, OR, XOR, NAND, NOR, and XNOR for handling Bipolar types.
Bipolar AND is as follows.

A half adder using a Bipolar type basic logic device looks like this
It is the same as the circuit of a normal basic logic device.
I haven't created an icon for the logical element yet, so it's a square box.

By using the Bipolar type, it is possible to know the completion of an operation.
In the following Bipolar Full Adder 4 signals, the Bipolar Full Adders are cascaded, so the output timing of the calculation results is different between the S0 and C output pins.

However, the Bipolar type shows that the information has not yet arrived, so the state can be easily detected.
This allows you to build a combinational circuit that operates at the maximum speed of the FPGA in which it is implemented.
The bit-type O pin is set to 1 when information arrives at both the A and B pins of the following Bipolar type.
This circuit can be cascaded using the X terminal.


The Bipolar type is now embedded in the SchemaHD application.
If you are downloading and using the ZIP file, please note that the ID is different from the Bipolar type built into SchemaHD.

Interface
Name ID in ZIP file ID in embedded parts
Onedaq44yn7357449s053m04wnh1cabq44yn7357449s053m04wnh1c
Zerox1ec6wz6amaq5fg0chr2ebxvgwacec6wz6amaq5fg0chr2ebxvgw
Bypolarhk5h3se2bjhvrermwn81kaddfgacfh3se2bjhvrermwn81kaddfg

Schema
Name ID in ZIP file ID in embedded parts
Bipolar BUFFERc95mr42mjfmhsy69zdr65d7nx9abtsf0jqfat9yzwt2wc8q4caw1
Bipolar NOTjkakt8h1tc9rycemtx196v2hxaabvbmbv1aqxttfacy8xmmwpaxa
Bipolar ANDd6zv12ggrh4bc93c9b1wk886hyabvk9y3qd2gxdcestbwjdb8a7w
Bipolar NANDp6rdjejkjrmce8kh45kx11shd7abvx9zswhvmpm8hdakgw8y6gg8
Bipolar ORdyerbt36wrbg61xeafqz3cgpxeabwb3vxcybt0vtv2cet3rrhzd5
Bipolar NORyy9pxwhpt5x933198jtdxa2z3yabwvxacdfz3v1fnph1xk3jk4wr
Bipolar XORjj1gcy8szkeyzntnvvqtg110qsabx5arahvcdr6yxww7v1rdg1bv
Bipolar XNORgb0fsxtk7pag26h3f4n5y6rc3zabxk1dpk5kqfjhjq6rq0kky1hb
Bipolar Voidvfxd7ck3r2qxq9486gyyscddwxabxws3wprgh7pxmwrmd5hcjbwc
Bipolar Onevbf1enxgpj2arebr3ymcbaqb7nabyb3wr5gae5mfh2xzw3m4y0q0
Bipolar Zerorcnw58mp1bbyp0vsb7v7539tphabymt7xhenhf1jr9rjjsbcjdk0
Bipolar Mergew9jmqqknk60se93jsqztp0m7d4abyz3w4fsgnadq5fgkrd3j7gr4
Bipolar Muxcx1ax50gn020fvvambnyx8h2x8abzjqnc0vvjq1w8zn6x7m2n7e3
Bipolar DeMuxn26ez8wzt85rbs8jk33gbent95abztxzfksxk9cfp6zd1m1g4d1m
Bipolar Validb3z4q9zdh4hw81094q9by0stx6abzzkmdg4sdy9bagqxzhvfd5jt
Bipolar Waitingtjrnrap92xacy50dqhrvg0fm93ac0tes8yxyd6y5q8gkmt0vmy1d
Bipolar Latchr3hdga783gkmmyn0r0krj0xajkac1gpn0wneaejnnr4dv3b6dspm
Bipolar Combiney5azamqzqjaj1smk7dzbbdp3mtac1wr9yhnz3mhnvsmkqgf6emah
Bipolar Separatekwmxgtsc9a6h6nv76qkxx535bkac2vvfnw5n3pfrtpg7a4gsvx1j
Bipolar Half Adderjts4tz58y7mbap3bwkn6bt64qzac3gazre5pw1xj0zwx9m3gf9rr
Bipolar Full Adderqpymtxha24ws9wv209s30tdkg6ac3tw2wtgsagbkrw9hff0hz6w9


We are planning a stream processing circuit using Bipolar type logic circuits.